The present invention relates to a synchronized clocking system wherein the basic clock frequency is selectable and the switch-over between the basic clock frequencies is accomplished without loss of synchronism between the various clocking units.
The present invention relates to an improvement in clocking systems such as that used in the Sperry Corporation 1100/90 data processing system. Such systems may include input/output processors and storage units operating on a four-phase 60 ns clock and instruction processors, scientific processors and high performance storage units operating on an eight-phase 60 ns clock. Each unit, i.e. processor or storage unit has an associated clock distribution module or modules for distributing clocking pulses to the logic circuits within the unit. The clock distribution modules are driven from a system master clock pulse source and each clock distribution module includes a plurality of clock pulse generators for generating the different phase pulses which are required for clocking the logic circuits of its associated processor or memory unit.
For purposes of uniformity of implementation the clock pulse generators are identical integrated circuits which are programmable to produce either four or eight phase clock signals. The clock pulse generators each include a four stage ring counter and an indicator. Generally speaking, the ring counter is stepped by the system clock pulses and the resulting output signals are gated to different clock phase output terminals of the clock pulse generator. Assuming that a clock pulse generator is programmed to produce four-phase clocking signals, the four output signals of the ring counter are applied to four sets of output terminals so that a clock pulse of a given phase appears at a given set of output terminals once for every fourth system clock pulse. If a clock pulse generator is programmed to produce eight-phase clocking signals then the four output signals of the ring counter are applied to eight output terminals. On one cycle of the ring counter its output signals are applied to four sets of output terminals of the clock pulse generator and on the next cycle its output signals are applied to four different sets of clock pulse generator output terminals. Thus, in a clock pulse generator producing an eight-phase clock, the first stage of the ring counter produces the phase 1 and 5 pulses, the second stage produces the phase 2 and 6 pulses, the third stage produces the phase 3 and 7 pulses, and the fourth stage produces the phase 4 and 8 pulses.
For maintenance purposes it may sometimes be necessary to operate the clock pulse generators of a given clock distribution module at a rate different from the normal frequency. For example, if an intermittent problem should develop the maintenance engineer may wish to operate the clock pulse generators of a given clock distribution module at a higher frequency so that the malfunction will occur more frequently, or permanently, if the problem is a marginal timing problem. On the other hand, the maintenance engineer may wish to operate the clock pulse generators at a lower frequency. If the problem persists at the lower frequency then the problem is not one of marginal timing but is instead probably a logic malfunction in the unit driven by the clock distribution module.
It is necessary that synchronization be maintained when the maintenance engineer switches between system clock frequencies. It is essential that the change-over be detected as soon as possible, the clock pulse generators stopped, cleared and then restarted so that they output the next phase following the one they were in at the time they were stopped.
The problem of selecting the restart phase is rendered more difficult since the clock pulse generators are capable of producing either four or eight phase outputs from a single four-stage counter and must align with the system clock. Thus, on restart it is necessary to know if the first phase pulse to be issued is to be, for example, a phase 1 or a phase 5 pulse if programmed as an 8-phase generator.